1. Field of the Invention
The present invention relates to a substrate voltage generating circuit of semiconductor memory devices and, more particularly, to a substrate voltage generating circuit for adjusting a substrate voltage in accordance with a refresh characteristic of the devices.
2. Description of the Prior Art
Insulated-gate field effect transistors (FETs) using metal-oxide-semiconductor (MOS) construction are known, ones of n-channel type (NMOS FETs) being constructed in p-type substrate or isolation wells, and ones of p-channel type (PMOS FETs) being constructed in n-type substrate or isolation wells. In a dynamic random access memory (hereinafter referred to as "DRAM") constructed on a substrate of p-type semiconductive material, capacitance is exhibited between the substrate and the bus connections at the lowest voltage to which the source electrodes of NMOS FETs generally are connected, which lowest voltage is conventionally designated as "ground" potential. A portion of this capacitance is attributable to the pn junctions formed between the p-type substrate and the n-type source diffusions of the NMOS FETS. The common practice is to use a substrate voltage generating circuit for generating a negative voltage, as referred to that "ground" potential, for application to the substrate of p-type semiconductive material. When the negative voltage generated in the substrate voltage generating circuit is applied to the substrate in the DRAM, the fluctuation of the threshold voltage of an NMOS FET caused by the body effect of the transistor can be minimized. Further, the application of the negative voltage to the substrate makes it possible to heighten a punch-through voltage and to reduce a junction capacitance thereby to improve overall operation speed of the device. At the same time, when a substrate voltage VBB is connected with a ground voltage terminal, an amount of a subthreshold current can be reduced and a forward-bias phenomenon caused due to undershoot of an input voltage can be suppressed thereby to protect the memory device. As noted from the above, the application of the negative voltage to the substrate of the DRAM ensures good performance of the memory device.
FIG. 1 is a circuit diagram illustrating the structure of the substrate voltage generating circuit used in a conventional DRAM. In FIG. 1, an oscillator 10 is enabled by an oscillating control signal .phi.EN being received and generates a square wave oscillating signal. A driver 20 connected to the output terminal of the oscillator 10 amplifies the oscillating signal and supplies the amplified signal to a charge pump 30. Then, the charge pump 30 is enabled in a period during which the oscillating signal is generated, and charges and pumps charge between the substrate and the ground bus connections, thereby generating the substrate voltage VBB having the negative voltage. The substrate voltage VBB is supplied as the negative voltage to the substrate. In addition, the substrate voltage VBB is applied to a voltage detector 40 which detects the substrate voltage VBB and, if the detected substrate voltage VBB rises above a constant reference voltage, generates an oscillating control signal .phi.EN. Accordingly, if the substrate voltage VBB does not maintain a constant negative voltage level, the voltage detector 40 generates the oscillating control signal .phi.EN for adjusting the substrate voltage VBB.
The voltage detector 40 is composed of a p-channel metal-oxide-semiconductor PMOS field-effect transistor (FET) 111 connected between a supply voltage VCC and a connection node 102 and having a gate electrode connected to the ground voltage VSS, an NMOS transistor 112 having a drain electrode connected to the connection node 102 and a gate electrode connected to a supply voltage VCC, a PMOS transistor 113 connected between a source electrode of the NMOS transistor 112 and an output node 101 and having a gate electrode connected to the output node 101, and a buffer amplifier 114 connected between the connection node 102 and the oscillator 10. The buffer amplifier 114 should have sufficient gain that its output signal is in one of two states depending on whether its input signal voltage is above or below a toggle point voltage. The buffer amplifier 114 can, for example, comprise a cascade connection of an even number of logic inverters, each of complementary-conductivity metal-oxide-semiconductor (CMOS) construction, receiving VCC as operating potential and having an input toggle point voltage of VCC/2.
In the FIG. 1 substrate voltage generating circuit the MOS transistors 111-113 function as a sensing means for developing a sensing voltage indicative of the level of the substrate voltage VBB, and the buffer amplifier 114 functions as a means for detecting whether that sensing voltage is more positive or more negative than a toggle point voltage, with the its output signal being in one of two logic states indicative of which condition obtains. In the operation of the sensing means, the PMOS transistor 111 is turned ON because its gate electrode is connected to the ground voltage VSS, the NMOS transistor 112 is turned ON because its gate electrode is connected to the supply voltage VCC, and the PMOS transistor 113 is turned ON because its gate electrode is connected to the substrate voltage VBB. Therefore, the MOS transistors 111-113 are in turn-ON states. A voltage is generated in the connection node 102 as determined by the potential dividing action among the channel resistances of the MOS transistors 111-113, which channel resistances are determined by the respective channel dimensions of these transistors. Thus, the buffer amplifier 114 is toggled in accordance with the sensing voltage level generated at the connection node 102 and thereby determines the logic state of the oscillating control signal .phi.EN.
That is, if the substrate voltage VBB is raised to be higher than a preset voltage, the voltage level detected at the connection node 102 becomes higher than the toggle point voltage level of the buffer amplifier 114. The oscillating control signal .phi.EN goes high to enable oscillation by the oscillator 10. The charge pump 30 is accordingly driven by the driver 30 to charge the substrate to a more negative substrate voltage VBB. However, if the substrate voltage VBB is at least as negative as the prescribed voltage, the voltage level detected at the connection node 102 becomes lower than the toggle point voltage level of the buffer amplifier 114. The oscillating control signal .phi.EN goes low, and oscillation by the oscillator 10 is disabled. Accordingly, the channel dimensions of the MOS transistors 111-113 are selected dependent upon the levels of the toggle voltage of the buffer amplifier 114 and the substrate voltage VBB level. In other words, in the case where the substrate voltage VBB is generated with the prescribed level, the channel dimensions of the MOS transistors 111-113 are selected so that the voltage level detected at the connection node 102 is just below the toggle point voltage level of the buffer amplifier 114. Then, the voltage detector 40 generates the oscillating control signal .phi.EN in order to bring the substrate voltage VBB down to the prescribed negative voltage and maintain the substrate voltage VBB at the prescribed negative voltage. Usually, the channel dimensions are chosen so that the offset voltage of the diode connected FET 113 approximates the desired substrate voltage VBB and so that potential dividing action is primarily between relatively high channel resistances of the PMOS FET 111 and NMOS FET 112. Arranging for potential dividing action to be primarily between relatively high channel resistances of the PMOS FET 111 and NMOS FET 112 compensates somewhat for process variation in the input signal toggle point of the buffer amplifier 114, supposing it to use a CMOS inverter as an input stage.
A variant of the voltage detector 40 known in the art replaces the diode-connected PMOS FET 113 with a diode-connected NMOS FET with its source electrode connected to the substrate. Another variant of the voltage detector 40 known in the art connects the gate of NMOS FET 112 to the ground voltage VSS instead of the voltage VCC. The voltage scaling network for substrate potential, used to supply input voltage to the buffer amplifier, is no longer of the nature of a potential divider but rather functions as a common-gate amplifier.
A known problem with the voltage detector 40 and these variants is that the channels of the FETs 111-113 provide a conduction path from the VCC bus to the substrate that tends to pull the substrate positive in potential, so the charge pump 30 consumes appreciable power to counteract this tendency. Normally, to try to minimize this problem, the channel dimensions of the FETs 111-113 those of are made so as to keep the resistances of their channels high when conductive. This is particularly so of FETs 111 and 112, which provide most of the potential-divider function.
In the DRAM which restores data stored in the memory cell by performing a refresh operation, the static refresh and dynamic refresh characteristics of the memory cell determine the production yield of the memory device. The static refresh characteristic is associated with a junction leakage current of the storage node of the memory cell. In other words, if the negative voltage applied to the substrate is lowered, the inverse voltage applied to the junction of the storage node is accordingly lowered, so that the junction leakage current can be reduced and the static refresh characteristic can be improved. On the other hand, the dynamic refresh characteristic is associated with isolation of the memory cells adjacent to each other. In other words, if the negative voltage applied to the substrate is lowered, the potential barrier between the storage nodes of the memory cells is accordingly raised, so that an isolation characteristic can be improved. Moreover, the semiconductor memory device embodies its own function by the combination of numerous logics. Accordingly, when fabricating the memory device, a great number of production processes can be implemented. At this time, the logics may respectively have features different from each other because of defects generated during the production processes. However, in the case of using the voltage detector 40 having the structure of FIG. 1, since the channel dimensions of the MOS FETs 111-113 have been fixedly determined, the voltage detector 40 generates the constant negative voltage irrespective of the different fabricating process and the refresh characteristic. As a result, there exists a problem that the production yield of the memory device is reduced because of inability to adjust the negative substrate bias during manufacturing of the DRAM.
Fusible links that can be interrupted or cut with a laser beam have been previously used for modifying various integrated-circuit configurations during integrated-circuit manufacturing.